And yet another beta:
Originally Posted by :
* CE-mode CIA interrupt delay decreased by 1 CPU clock cycle, tst.b CIAICR immediately followed by move.w #x,INTREQ didnīt clear the interrupt in some situations
* disk DMA used generic memory access routines, not chip access routines (could DMA to/from any memory address, not just chip ram)
* "Z3 fake chip" added, "unlimited" chip ram size. (technically it adds another z3 fast ram board that UAE boot rom changes to MEMF_CHIP|MEMF_PUBLIC|MEMF_LOCAL and removes normal chipset DMA addressing limits)
* two directory filesystem crash fixes (related to opening non-existing files or directories, broken during C++ conversion)
* CD32 state restore didnīt work if CD32 configuration was not pre-selected
* save POT capacitorsī charge status to statefile
* disk read DMA wordsync should not skip first syncword if bit stream is already aligned (Starglider 2 original) REVERTED
* on the fly cycle-exact switching broke few betas ago
* use early blitter finished state emulation only in 68000 cycle exact modes, 68020 "CE" can execute blitter busy check followed by write to blitter register really too quickly
